Along with the development of semiconductor technology, the VLSI process has advanced toward the deep submicron field. Accordingly, the line width, line space, and the size of contact holes have all shrunk such that controlling the dimensions of the semiconductor devices, and in particular, the critical dimensions, is more difficult than ever.
To make the fabrication process for VLSI stable and reliable, it is very important to keep the deviations of the critical dimensions within a tolerant range. In order to meet such requirements, the process parameters must be set up by practical CD experiments. Therefore, CD structures, such as verniers and the like, are designed for use with automated inspection tools such as scanning electron microscopes (SEMs) to assure that real pattern CD values are within the acceptable range of designed targeted CD values.
Fabrication of VLSI devices typically involves the use of a plurality of masks which define circuit features thereon. Maintaining the dimensional conformity between defined circuit features on such masks is highly desirable. For example, maintaining the critical dimensions as between multiple masks is essentially required in order to ensure that the ultimately-formed integrated circuitry is standard in its performance and operation.
One way that mask-defined features have been checked for dimensional conformity in the past has involved inspecting each subsequently rendered mask image for its specific feature dimensions to ensure compliance with particular design parameters. This process is particularly time-consuming because each rendered mask image must be checked. This can increase processing time and thereby decrease throughput.
Accordingly, this invention arose out of concerns associated with improving the methods by which integrated circuitry is formed. In particular, this invention arose out of concerns associated with improving methods for inspecting for mask-defined, feature dimensional conformity between multiple masks.